1. Field of the Invention
The invention relates to an image processing chip and related method thereof, and more particularly, to an image processing chip capable of separating video signals and synchronization signals and the related method thereof.
2. Description of the Prior Art
Generally, a monitor can process and display a received video signal according to a horizontal synchronization signal and a vertical synchronization signal. In certain transmission interfaces with specific standards, the horizontal synchronization signal and the vertical synchronization signal are firstly integrated into a composite sync signal, and the composite sync signal is then attached to an image signal. For instant, a G signal of the RGB signal is associated with a green color, or the Y signal of the YPbPr signal is associated with a luminance. The above-mentioned green signal with the synchronization signal is also referred to as the SOG signal (i.e., sync on G), and the luminance signal with the composite synchronization signal is also referred to as the SOY signal (i.e., sync on Y). In order to illustrate these concepts conveniently, the following video signals, which include the composite synchronization signal, are referred to as the composite signal.
Please refer to FIG. 1. FIG. 1 is a circuit diagram of a conventional image processing chip 10. The image processing chip 10 sets two pins 12 and 14 for receiving the composite signal. The internal circuit (not shown) coupled to the pins 12 and 14 is utilized to collect the synchronization signal and the image signal from the composite signal respectively. The external portion of the image processing chip 10 includes capacitances 22 and 24, and a DC bias rebuilding circuit 16. The DC bias rebuilding circuit 16 adjusts the composite signal to a predetermined voltage level, and then obtains the synchronization signal from the internal circuit that is coupled to the pin 12. In this case, the internal circuit coupled to the pin 14 will latch the image signal from the composite signal according to the synchronization signal. Due to the pins 12 and 14 having two capacitances 22 and 24, the composite signal received from the pin 14 will not be affected by the DC bias rebuilding circuit 16.
The above-mentioned method of utilizing two pins to receive the same composite signal is quite uneconomical. Moreover, when the image processing chip 10 is designed to receive the video signals with a plurality of sources, the amount of pins required for the task will obviously increase. Therefore, the chip size and the cost to manufacture the chip will significantly increase.